Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Non-volatile memory is memory that can retain its data values for some extended period without the application of power. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming of charge storage or trapping layers or other physical phenomena, determine the data value of each cell. By defining two or more ranges of threshold voltages to correspond to individual data values, one or more bits of information may be stored on each cell. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, cellular telephones, and removable memory modules, and the uses for non-volatile memory continue to expand.
Flash memory typically utilizes one of two basic architectures known as NOR flash and NAND flash. The designation is derived from the logic used to read the devices. In NOR flash architecture, a column of memory cells are coupled in parallel with each memory cell coupled to a bit line. In NAND flash architecture, a column of memory cells are coupled in series with only the first memory cell of the column coupled to a bit line.
Flash memory is often based on the Floating-Gate Avalanche-Injection Metal Oxide Semiconductor (FAMOS transistor) which is essentially a Complementary Metal Oxide Semiconductor (CMOS) Field-Effect Transistor (FET) with an additional conductor layer suspended between the gate and source/drain terminals. Such flash cells are thus similar to a standard MOSFET transistor, except that they have two gates instead of just one. One gate is the control gate (CG) like in other MOS transistors, but the second is a floating gate (FG) that is insulated all around by a dielectric layer. The FG is between the CG and the substrate. Because the FG is isolated by its insulating oxide layer, it is capable of trapping electrons placed in it and thus storing information.
When electrons are trapped on the FG, they modify (partially cancel out) an electric field coming from the CG, which modifies the threshold voltage (Vt) of the cell. Thus, when the cell is “read” by placing a specific voltage on the CG, electrical current will either flow or not flow between the cell's source and drain connections, depending on the Vt of the cell. This presence or absence of current is sensed and translated into 1's and 0's, reproducing the stored data values of the cells.
Programming efficiency in flash memory, which is defined as a ratio of transistor gate current to programming drain-source current, is an important factor in determining power consumption in flash memories. The programming efficiency of flash memory cells, which utilize hot-electron injection, has been enhanced by applying a substrate bias.
Mechanisms of hot-electron injection in a floating gate transistor during a program operation are well known. The channel hot electron (CHE) component comes from energetic channel electrons which are accelerated by lateral electric fields along a channel of the floating gate transistor. A channel initiated secondary electron (CHISEL) component comes from energetic electrons that are generated by hole impact ionization in the substrate and accelerated by vertical electric fields.
A gate current (Ig) by hot-electron injection in a program mode can be expressed as Ig=ICHE+ICHISEL. The ICHE component comes from energetic channel electrons which are accelerated by a channel electric field. The ICHISEL component comes from energetic electrons that are generated by hole impact ionization in the substrate and accelerated by a vertical electric field.
Known techniques for writing electrons onto the floating gate are still very inefficient. The drain current is on the order of a million times the gate current, or only about one in every million electrons flowing down the transistor channel is injected or results in an electron being injected on to the floating gate. This requires that a high drain current be used during writing, resulting in excessive power dissipation.
A BiMOS structure has been used to study the basic physical mechanisms of electron trapping in MOS gate oxides; see FIG. 9. The test structure 900 included a gate 902, a gate oxide layer 904, source 906 and drain 908. A buried bipolar emitter-base diode, formed of layers 912 and 914 in substrate 905, was used to inject electrons 916 which were accelerated in a surface depletion region and injected into the gate oxide 904. Excess electrons were collected by reverse biasing the drain 908 and/or source 906 regions.
For the reasons stated above, and for other reasons which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative memory architectures for improved efficiency and reduced power consumption in programming a non-volatile memory cell.